Capacitance-Toggle Rate Weighting to Optimize Switching Power at Placement Stage of VLSI Conception
نویسندگان
چکیده
منابع مشابه
Capacitance and Power Modeling at Logic-Level
Accurate and fast power estimation of CMOS circuits during the design phase is required to guide power optimization techniques employed to meet stringent power specifications. Logic-level power estimation tools, such as those available in the SIS and POSE frameworks are able to accurate calculate the switching activity under a given delay model. However, capacitance and delay modeling is crude....
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ژورنال
عنوان ژورنال: Journal of Engineering and Applied Sciences
سال: 2019
ISSN: 1816-949X
DOI: 10.36478/jeasci.2019.3243.3249